The ever-increasing demand for faster image processing systems dictates that state-of-the-art image processors execute instructions and process data in the minimum amount of time. Over the years, image processor speeds have been increased in a variety of ways, including, increasing the speed of the clock that drives the processor, reducing the number of clock cycles required to perform a given instruction, reducing the number of gate delays incurred while executing an instruction, increasing the number of instruction pipelines, and the like.
An instruction pipeline is a series of separate instruction processing stages. Each stage is independent and is optimized to perform a specific portion of the overall instruction processing. Thus, instructions may be fed into the first stage of the pipeline and each stage performs a specific portion of the instruction, much like an assembly line. It is typically not necessary for one instruction to finish processing before the next instruction is loaded into the pipeline. Multiple instructions may therefore be loaded into the instruction pipeline (e.g., a five stage instruction pipeline may contain up to five instructions at one time).
The instruction pipeline concept has been extended to multiple pipeline architectures. In a multiple pipeline architecture, an instruction decoder feeds instructions to two or more instruction pipelines. The instruction decoder may select a particular pipeline based on which instructions are already in each pipeline, how fast the instructions are expected to flow through the remaining pipeline stages, the “speciality” of the particular pipeline, or the like.
Multiple pipeline architectures are well suited for processing two-dimensional and three-dimensional image data (“graphics processing”). Graphics processing techniques commonly describe images in terms of the dimensions of the objects to be represented. For instance, an image processing system may represent objects in two-dimensional space (e.g., having x and y coordinates, wherein the graphics are said to be “two-dimensional”), and three-dimensional (e.g., having x, y, and z coordinates, wherein the graphics are said to be “three-dimensional”).
Graphics processing systems commonly display two-dimensional and three-dimensional graphics representations of objects on a two-dimensional image display screen (e.g., computer monitor, television, etc.). These systems “break down” the graphical representation of an object into graphics primitives (e.g., points, lines, quadrilaterals, triangle strips, polygons, etc.) and process the same in one of two image-processing pipelines. If the object is represented in two-dimensional image space, then it is processed in a two-dimensional image pipeline to generate successive two-dimensional image frames. If the object is represented in three-dimensional image space, then it is processed in a three-dimensional image pipeline to render successive three-dimensional image frames.
For instance, the primitives of a three-dimensional object to be rendered are defined in terms of primitive data, so that when the primitive is a triangle, its primitive data may be defined in terms of the X, Y, Z and W coordinates of its vertices, as well as the red, green and blue and alpha color values of each vertex (of course, additional primitive data may be used in specific applications). The three-dimensional pipeline interpolates the primitive data to compute the coordinates and colors of display screen pixels that represent each primitive, and the R, G and B color values for each pixel.
The availability of graphics processing is becoming increasingly important, and not only in entertainment related applications (e.g., video games, DVD systems, direct broadcast satellites, production quality film animation tools, etc.), but in many other broader areas, such as education, video conferencing, video editing, interactive user interfaces, computer-aided design and computer-aided manufacturing (“CAD/CAM”), scientific and medical imaging, business applications, and electronic publishing, among others.
Conventional image processors are commonly built with separate functional units for handling two-dimensional (e.g., decoder, quantization controller, motion compensation controller, etc.) and three dimensional image processing operations (e.g., a geometry accelerator, a rasterizer, etc.). A primary disadvantage to such implementations is the relative size of the processing logic associated with the functional units necessary to provide the above-described multiple pipelined architecture.
Further, there are symmetries among various processes performed by certain ones of the functional units associated with each of the two image processing pipelines, however, contemporary implementations fail to utilize the same to implement multi-modal units that meet the functional requirements of both two- and three-dimensional image processing pipelines.
Therefore, while an ongoing need exists in the art for improved image processors that include multiple instruction pipelines, a particular need has arisen in the art for a multiple instruction pipeline image processor that efficiently utilizes such inherent symmetries in implementing two- and three-dimensional image processing pipelines, thereby reducing the overall number functional units, and chip area or board space required to support the same.